Then, in January 2024, the dormant fab was booted up again. Intel funneled billions into the facility, including $500 million ...

TSMC (Taiwan semiconductor) has a major multi-year plan to create rectangular substrate (510 millimeters by 515 millimeters) with over triple the usable area of current round wafers. The rectangular ...

Intel disclosed several chip packaging breakthroughs at the Electronic Components Technology Conference (ECTC), outlining the technical merits of multiple new chip packaging techniques. We spoke with ...

Thanks to the AI tsunami, demand for AI chips from all sectors is continuing to surge. The Chip-on-Wafer-on-Substrate (CoWoS) architecture that dominates existing 2.5D and 3D packaging technologies is ...

SEM (scanning electron microscope) images of test chip designed by Deca. Upper left show a molded multi-chip fan-out package with close-ups of the embedded die right and below The last time I wrote ...

Austin, March 13, 2026 (GLOBE NEWSWIRE)-- High-End Semiconductor Packaging Market Size & Growth Insights: According to the SNS Insider, “The High-End Semiconductor Packaging Market size was valued at ...

Aug 1 (Reuters) - Taiwanese chipmaker TSMC 2330.TW has developed the most expansive arsenal of patents surrounding advanced chip packaging, followed by Samsung Electronics 005930.KS and then Intel ...

With the consumer electronics market approaching saturation, panel manufacturers from Taiwan and China are seeking new avenues for growth. Firms like BOE and Innolux are shifting toward advanced ...

The field of electronics, particularly integrated circuit (IC) technology, has advanced rapidly in recent years. With the development of 5G/6G mobile technology, semiconductor devices are evolving to ...

Designed for nanometer-scale silicon ICs, a new wire-bond chip-packaging process–called Pad on I/O–by chip manufacturer LSI Logic (Milpitas, CA) places bond pads directly on active copper/low-K ...