Electronic Design

ESD Test Epuipment – HBM Device Failure- The Scourge of Static-Sensitive Operations

This close examination of S20.20 reveals the key ingredients to a successful ESD control program. Multinational manufacturing corporations are racing to pursue the cost benefits of economic geography.
EDN

Signal Chain Basics #91: The Difference Between HBM & IEC 61000-4-2 ESD Immunity

The electrostatic discharge (ESD) ratings in component data sheets often confuse system designers by not specifying the actual standard to which a component was tested. The following explains the ...
Business Wire

Faraday Delivers System-Level ESD Protection Service to Reduce ASIC Time-to-Market

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today introduced its system-level ESD (electrostatic discharge) protection ...
Semiconductor Engineering

Assessing ESD Sensitivity Of Interface IP Using Charged Device Model

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, especially from the completion of the silicon wafer processing to when the device is assembled ...
Electronic Design

Is System-Level ESD Testing Valid for ICs?

A study to evaluate the applicability of IEC-61000-4-2 testing at the semiconductor device level finds that results depend more on variations in test setup than in ESD sensitivity. Donna Robinson-Hahn ...
EDN

Matching ESD protection to process geometry

Advanced CMOS process technologies enable IC designers to deliver higher performing devices, but also increase the need for extra board-level ESD protection to ensure the reliability of the end ...