Nature

Low-Density Parity-Check Decoder Architectures and Algorithms

Low-Density Parity-Check (LDPC) decoder designs have undergone significant evolution, driven by the need for high-throughput, low-complexity and energy-efficient ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
Design-Reuse

LDPC Decoder IS-GPS-800D IP

The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forward Error ...
Design-Reuse

LDPC IP Core

This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizable Verilog IP. The system was designed to be used in conjunction ...
New Electronics

AccelerComm develops LDPC Decoder for Intel’s FlexRAN

AccelerComm, the company specialising in optimisation and latency reduction IP, has announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The solution is ...